# GOAL_6 - Prevent Address Collapse and Actually Test Explicit Memory ## Status Planned ## Experiment Experiment 006 ## Research Objective GOAL_5 attempted to test explicitly addressable detachable memory. It did not successfully test that hypothesis. The key-value memory collapsed during training so that essentially every query selected the same memory slot. Across the trained GOAL_5 memory: 384 of 384 fact-probe accesses selected slot 63. 4,285 of 4,287 composition accesses selected slot 63. Distinct dominant slots across all facts: 1 of 128. The resulting memory read was effectively input-independent. The architecture therefore behaved approximately like a learned constant bias injected at layer 18 rather than an addressable memory. GOAL_6 has one purpose: Make addressing carry information by construction, then determine whether the explicit-memory hypothesis works when the memory actually addresses different contents. ## Core Hypothesis GOAL_5 failed because the addressing distribution sharpened before the query-key system differentiated. If premature addressing collapse is prevented during training, different facts should develop different stable memory-address patterns. If that occurs, the explicit memory can finally be tested for: Recall. Recursive memory access. Composition. Interference. ## Primary Research Question Can the GOAL_5 explicit key-value memory learn input-dependent addressing without collapsing to one slot? ## Secondary Research Question If addressing becomes genuinely input-dependent, can a frozen Qwen3-0.6B use that memory for recall and recursive two-hop reasoning without the interference seen in previous mechanisms? ## Critical Distinction GOAL_6 is not primarily an accuracy experiment. Its first success condition is addressing differentiation. Do not interpret recall, composition, or interference until addressing has been shown to carry information. The causal sequence under test is: Informative hidden state -> differentiated query -> differentiated memory address -> correct memory read -> recall -> second query from reasoning state -> second memory read -> composition The experiment must identify exactly where this sequence stops. ## Baseline Failure to Reproduce GOAL_5 is the negative reference. GOAL_5: 128 slots. Query dimension 128. Value dimension 512. Layer 18 insertion. 739,456 memory parameters. Loss 6.4254 -> 2.9058. Recall 0/48. Composition 0/24. Interference 0.2500. Distinct dominant slots: 1/128. Top slot share: 1.0000 for every fact. The GOAL_6 mechanism must demonstrate that it does not reproduce this addressing collapse before full training is allowed to continue. ## Architecture Preserve the GOAL_5 architecture unless a change is explicitly required to prevent address collapse. Keep: 128 key-value slots. Query/key dimension 128. Value dimension 512. Single insertion point at decoder layer 18. Same query source. Same readout path. Same gate. Same frozen base model. Same memory parameter budget where possible. Do not change placement. Do not change slot count. Do not change dimensions. Do not add additional insertion layers. The independent variable is the addressing-training mechanism. ## Required Change Introduce an anti-collapse training mechanism that prevents the softmax address distribution from becoming globally concentrated on one slot before query-key differentiation develops. Use one coherent anti-collapse recipe. Do not run a broad sweep. Preferred recipe: 1. Temperature-controlled addressing. 2. A batch-level slot-utilization regularizer. The purpose is not to force uniform slot use forever. The purpose is to prevent one slot from becoming the universal answer before different inputs develop different addresses. ## Temperature Use: scores = similarity(query, keys) / temperature Begin training with a temperature that keeps addressing relatively soft. Reduce temperature gradually during training. Choose one reasonable schedule before the full run. Document: Initial temperature. Final temperature. Schedule. Do not tune the schedule after seeing final evaluation results. ## Slot-Utilization Regularization Add a small regularization term based on the aggregate addressing distribution across training examples. The regularizer should discourage global single-slot collapse. It must not require every individual query to use all slots. It must not require exactly uniform slot usage. It must not assign symbolic facts to predetermined slots. The memory must still discover its own organization. Conceptually: total_loss = language_model_loss + lambda * address_regularization The regularization should operate on aggregate addressing behavior, not force each individual query to have high entropy indefinitely. Document the exact formulation. ## Important Constraint Do not solve the problem by manually assigning each fact to a slot. Do not provide slot labels. Do not supervise the correct slot. Do not hash entity names into addresses. Do not use the synthetic world structure to construct addresses. Addressing must remain learned from the model state. GOAL_6 asks whether learned addressing can be made viable, not whether an externally indexed lookup table works. ## Initialization Review the GOAL_5 initialization dynamics before implementation. GOAL_5 used a zero-initialized readout. At initialization this caused the upstream query, key, and value pathways to receive no useful gradient until the readout moved away from zero. This may have contributed to collapse. GOAL_6 may change the readout initialization if required to ensure useful addressing gradients exist from the beginning. If changed: Use a small non-zero initialization. Document it. Measure initial logit perturbation. Ensure gate = 0 remains exactly isolated. Do not introduce a large initial residual perturbation. This is part of the anti-collapse recipe, not a separate architecture sweep. ## Addressing Metrics Addressing behavior is now a first-class experimental metric. For every fact probe record: Top slot. Top weight. Top 3 slots. Top 3 weights. Entropy. Query norm. Margin between top-1 and top-2 scores. Where practical, record the similarity between addressing distributions for repeated phrasings of the same fact. ## Addressing Success Criteria A successful address system must satisfy more than "more than one slot was used." Measure: Distinct dominant slots. Global top-slot share. Per-fact dominant slot consistency. Between-fact address diversity. Within-fact address consistency across paraphrases. The desired qualitative behavior is: Same fact or entity relation -> similar address pattern. Different facts -> meaningfully different address patterns. Do not require one fact per slot. Multiple related facts may legitimately share slots. ## Anti-Collapse Training Gates Do not blindly run 30 epochs. Probe addressing during training. Save and inspect checkpoints at minimum around: Epoch 2. Epoch 4. Epoch 6. Epoch 12. Then later checkpoints if training continues. ## Early Stop Gate At the early checkpoints, probe the existing fact set. Stop the experiment early if addressing has clearly reproduced GOAL_5 collapse. A strong collapse condition is: Distinct dominant slots <= 2 and/or One slot receives more than 80 percent of dominant selections across the fact probes. Use judgment around transient early behavior. The purpose is to avoid spending 30 epochs on an obviously collapsed memory. If addressing is becoming more differentiated over successive early checkpoints, allow training to continue. Document the decision. ## Positive Addressing Gate Before interpreting recall or composition as a test of explicit memory, establish that addressing is genuinely input-dependent. A positive result should show: More than trivial slot diversity. No universal dominant slot. Stable address tendencies for repeated versions of the same fact. Meaningful differences between unrelated facts. If these conditions are not met, classify the run as another addressing failure. Do not claim that explicit memory itself failed. ## Base Model Use exactly the existing pinned Qwen3-0.6B revision. Keep: Same Jetson. Same dtype. Same eager attention backend. Same tokenizer. Same generation settings. Same seed 1337. Same synthetic world. Same training examples. Same recall set. Same composition set. Same control set. Same evaluation parser. ## Isolation Requirements Before training verify: All Qwen parameters frozen. Only memory parameters trainable. gate = 0 gives frozen-base logits. Randomized memory with gate = 0 gives frozen-base logits. gate = 1 proves the branch is connected. Removing the memory restores frozen-base logits. Base fingerprint remains unchanged. Do not proceed if isolation fails. ## Base Gate Revalidate the frozen base: Recall 0/48. Composition 0/24. Control 9/12. If these differ from the established baseline, stop. ## Training Data Use exactly the existing 144 per-fact training examples. Do not add: Composed answers. Control questions. Slot supervision. Address labels. Negative retrieval examples. New synthetic facts. The training information content must remain unchanged. ## Training Train only the memory mechanism. Keep the established optimizer and training configuration except for changes explicitly required by the anti-collapse addressing recipe. Document every difference from GOAL_5. Do not use Transformers Trainer. ## Evaluation Stage 1 - Addressing Addressing is evaluated first. Answer: Did different facts produce different memory addresses? Did paraphrases of the same fact produce similar addresses? Did the address distribution remain non-collapsed? How many slots meaningfully participate? Is slot utilization structured or merely random? If addressing fails, stop the scientific interpretation there. Recall and behavioral metrics may still be recorded, but do not proceed into expensive thinking-mode evaluation unless it provides clear diagnostic value. ## Evaluation Stage 2 - Recall If addressing passes the positive gate, evaluate recall. Target: Recall >= 0.90. Analyze incorrect recall in relation to memory addressing. Determine whether failures result from: Wrong address. Correct address but wrong stored value. Correct memory read but bad integration. ## Evaluation Stage 3 - Composition If addressing works and recall is meaningfully above baseline, run thinking-mode composition. Measure: Hop-1 intermediate in trace. Memory accesses before hop 1. Memory accesses after hop 1. Address selected after hop 1. Hop-2 radiation in trace. Final answer. This is the experiment GOAL_5 intended to reach. ## Recursive Addressing Test For each composition item determine: 1. Was the correct hop-1 fact retrieved? 2. Did the hop-1 intermediate enter the reasoning trace? 3. Was memory subsequently queried from the new reasoning state? 4. Did the address distribution change appropriately? 5. Did the new query select memory associated with hop 2? 6. Was the correct hop-2 value returned? 7. Did the final answer use it? This should produce a failure taxonomy. ## Failure Taxonomy Classify every composition item into one of: No hop-1 retrieval. Hop-1 retrieved, no meaningful second query. Second query issued, wrong address. Correct address, wrong memory value. Correct memory value, lost during integration. Correct two-hop chain, wrong final answer. Success. ## Evaluation Stage 4 - Interference Measure the established control set. Report: Control accuracy. Accuracy interference. Textual churn. Substantive churn. Regressions. Repairs. Leakage. Unicode-aware leakage must now be reported alongside the historical ASCII-compatible metric. Do not silently change historical results. ## Generation Stability Record: Mean reasoning tokens. Median reasoning tokens. Min and max. Truncations. Immediate-abort generations. Loopiness. GOAL_5 showed a bimodal failure with many 3-token aborts and several 1024-token runaways. Explicitly test whether this behavior disappears when addressing becomes informative. ## Gate Sweep Only after primary evaluation, if the trained memory contains actual knowledge. Evaluate: gate = 0. gate = 0.25. gate = 0.5. gate = 1. Do not interpret a gate sweep as useful if recall remains zero. ## Detachability Verify: Enabled. Disabled. Re-enabled. gate = 0 must restore frozen behavior. If memory successfully learned knowledge: Disabling should remove recall. Re-enabling should restore recall. Base weights must remain unchanged. ## Historical Comparison Compare GOAL_6 with: LoRA rank 4. LoRA rank 8. LoRA rank 16. GOAL_4 residual memory. GOAL_5 collapsed explicit KV memory. Include: Memory parameters. Address diversity. Recall. Composition. Hop-1. Hop-2. Control. Interference. Substantive churn. Leakage. Reasoning tokens. Truncations. ## Primary Success Outcome ### Outcome A - Addressing and Memory Work Addressing is differentiated. Recall >= 0.90. Composition significantly exceeds chance. Interference <= 0.10. Recursive second lookup is demonstrated. Interpretation: Explicit addressable memory is a viable direction. This would be the strongest result of the project so far. ## Outcome B - Addressing and Recall Work, Recursive Access Fails Addressing is differentiated. Recall is high. Interference is acceptable. Hop 1 works. Second lookup fails. Interpretation: The memory store is viable. The remaining bottleneck is recursive query formation from intermediate reasoning state. This directly returns the project to the original GOAL_5 question. ## Outcome C - Addressing Works but Recall Fails Different inputs reliably produce differentiated addresses. The memory still cannot return useful facts. Interpretation: Address collapse has been solved. The next bottleneck is value learning or readout integration. Do not blame addressing. ## Outcome D - Addressing Works but Interference Remains High The memory stores and addresses information. Control behavior is still heavily disturbed. Interpretation: Even a narrow, informative internal memory interface materially perturbs the frozen reasoner. This would be strong evidence against this family of internal write mechanisms. ## Outcome E - Address Collapse Repeats The same small set of slots dominates nearly all facts. Recall remains poor. Interpretation: The current differentiable key-value training approach is not viable under this setup. Do not run another softmax-addressing tweak automatically. This should trigger reconsideration of the addressing mechanism itself. ## Required Final Questions The final report must answer: 1. Did GOAL_6 prevent the GOAL_5 single-slot collapse? 2. How many memory slots became meaningfully active? 3. What fraction of fact probes selected the most common slot? 4. Are addresses stable across paraphrases of the same fact? 5. Are addresses meaningfully different across different facts? 6. Did the memory learn the synthetic world? 7. What recall was achieved? 8. Where do recall failures occur in the address-read-integrate chain? 9. Does hop-1 retrieval work? 10. After hop 1, does the reasoning state generate a different meaningful memory query? 11. Does the second query retrieve the correct hop-2 information? 12. Is composition significantly above chance? 13. What is the accuracy interference? 14. What is the substantive behavioral churn? 15. Does Unicode-aware or exact synthetic-world leakage occur? 16. Did the GOAL_5 abort/runaway generation pathology disappear? 17. Does gate = 0 reproduce frozen behavior? 18. Does disabling memory remove learned knowledge? 19. Does re-enabling restore it? 20. Did solving address collapse improve useful behavior rather than merely change slot statistics? 21. Where is the new bottleneck? 22. Does the evidence justify another explicit-memory experiment? ## Explicitly Out Of Scope Do not: Sweep temperatures. Sweep regularization strengths. Sweep memory sizes. Sweep insertion layers. Sweep query dimensions. Try multiple addressing algorithms. Assign facts to slots manually. Use external retrieval. Use vector databases. Add Memory B. Change the world. Add composed training examples. Train the base model. Return to LoRA. Build production infrastructure. ## Deliverables Create: results/experiment_006/ At minimum: experiment_006_report.md methods.md architecture.md anti_collapse_recipe.md base_isolation_validation.md results.json training logs addressing_checkpoints.json memory_slot_analysis.json memory_access_analysis.json memory_access_trace.json trace_analysis.json composition_failure_taxonomy.json behavioral_churn.json leakage_analysis.json detachability_validation.md gate_sweep.json if applicable Do not modify Experiments 000 through 005 artifacts. ## Exit Condition Run one anti-collapse explicit-memory configuration. Do not tune it after observing the result. If addressing clearly collapses at an early checkpoint, stop training and report. If addressing differentiates, complete recall, composition, interference, and recursive-access evaluation. Then stop. Do not implement another variant. Produce the report and wait for review. ## Operating Principle GOAL_5 built an addressable memory but gradient descent turned every address into the same address. GOAL_6 asks a narrower question: Can we preserve information in the address? Only after that is demonstrated can we legitimately ask whether the frozen reasoner can use explicit dynamic memory.