# GOAL_7 - Can the Address Itself Learn Identity?

Experiment 007

## Status

Not started.

## Core question

Can an explicit memory attached to a frozen reasoning model learn stable,
information-bearing addresses when address formation is trained directly rather
than being left for next-token prediction to discover?

GOAL_5 and GOAL_6 did not actually test useful addressability.

GOAL_5 collapsed because the address gradient path was initially starved.

GOAL_6 opened that gradient path and added an anti-collapse objective, but the
objective distributed soft probability mass rather than making addresses
input-dependent.

At the GOAL_6 stopping point:

    effective soft-usage slots: approximately 21
    distinct dominant slots across 24 facts: 1
    dominant-slot share: 1.0000

The memory therefore remained functionally unaddressed.

GOAL_7 changes the training signal rather than tuning the same mechanism.

The address will now be trained explicitly to encode fact identity.

The language-model objective is not allowed to be the sole teacher of addressing.


## Primary hypothesis

If addressing receives a direct supervisory signal requiring different facts to
produce distinguishable addresses while paraphrases of the same fact produce
consistent addresses, then the collapse observed in Experiments 005 and 006 should
disappear.

The important variable is not:

    how many slots carry probability mass?

It is:

    does the selected address contain information about the input?


## Null hypothesis

Even with explicit address supervision, the frozen model representation at the
chosen memory insertion point cannot be mapped reliably into stable,
fact-discriminating addresses.

If this happens, the current explicit-memory branch should be reconsidered rather
than repeatedly tuning addressing losses.


## Scope

This experiment tests ADDRESS FORMATION FIRST.

It does not begin by optimizing:

- recall
- composition
- recursive retrieval
- interference
- gate strength
- temperature schedules
- memory capacity

Those are downstream questions.

The first gate is whether meaningful addressing exists at all.


## Architecture

Start from the explicit KV memory implementation used in Experiments 005 and 006.

Do not create an unrelated architecture unless implementation evidence proves the
existing mechanism cannot support this experiment.

Preserve:

- frozen Qwen3-0.6B base model
- same pinned model revision
- same synthetic world
- same seed
- same insertion layer unless technically impossible
- same query dimension
- same slot count
- same instrumentation
- detachable memory
- gate = 0 exact base behavior
- unchanged base-weight fingerprint

The key change is the ADDRESS TRAINING OBJECTIVE.


## Address supervision

Each underlying memory fact must have an identity.

Examples expressing the same fact must share that identity.

Different facts must have different identities.

The training objective must therefore encourage:

    same fact, different phrasing -> same address

and:

    different fact -> different address

The implementation may use explicit slot targets, a classification objective,
contrastive address learning, or another simple supervised formulation.

Choose ONE mechanism before running the experiment.

Do not sweep mechanisms after observing results.

Document the choice and rationale in:

    results/experiment_007/address_training_recipe.md


## Important design constraint

Do not confuse slot assignment with useful addressing.

A trivial mapping based on training-example order, sequence position, or another
artifact is not acceptable.

The address must be derived from the model representation produced by the factual
input.

Paraphrases must therefore be used as a generalization test.


## Required address dataset

Construct address-training and address-evaluation examples from the existing world.

For every underlying fact:

- multiple phrasings may be used for address training
- at least one held-out paraphrase must not appear in address training

No held-out address-evaluation question may appear verbatim in training.

Assert this programmatically.


## Phase A - Address-only training

Train the query/key addressing pathway using the explicit address objective.

During this phase, do not allow value/readout learning to hide address failure.

The experiment must make it possible to determine whether the address itself
learned before asking whether retrieved values are useful.

Record:

- address loss
- distinct dominant slots
- dominant-slot distribution
- between-fact address entropy
- within-fact paraphrase agreement
- address accuracy if explicit slot labels are used
- score margins
- soft read entropy
- effective soft slot usage

Most importantly, report BOTH:

    soft usage diversity

and:

    hard address diversity

GOAL_6 demonstrated that these are not interchangeable.


## Positive addressing gate

Addressability passes only if all of the following are true on held-out paraphrases:

1. More than one dominant slot is used across facts.

2. Different facts produce meaningfully differentiated addresses.

3. Paraphrases of the same fact produce substantially more consistent addresses
   than unrelated facts.

4. No single dominant slot accounts for more than 50 percent of facts.

5. The addressing result cannot be explained by soft-mass diversity while the
   argmax remains constant.

If explicit target slots are used, additionally require:

    held-out paraphrase address accuracy >= 0.90

If the chosen formulation does not produce a literal classification accuracy,
define an equivalent quantitative criterion BEFORE training and record it in
address_training_recipe.md.


## Hard stop A

If the positive addressing gate fails:

STOP.

Do not train values.

Do not evaluate composition.

Do not change temperature.

Do not change regularization strength.

Do not change slot count.

Do not try a second addressing loss.

Diagnose the failure, write the report, and end GOAL_7.

This is evidence that the selected direct-address training mechanism failed.


## Phase B - Value learning

ONLY if Phase A passes.

Freeze or otherwise preserve the successfully learned address mapping.

Then train the memory value/readout pathway to associate the learned addresses with
the existing facts.

The objective of this phase is simple:

    correct address -> correct stored information

Do not introduce composition examples.

Do not introduce control questions into training.


## Recall gate

After value training, evaluate the existing 48-question recall set.

Target:

    recall >= 0.90

Also record addressing for every recall question.

This lets us distinguish:

    wrong address
    correct address but wrong value
    correct retrieval but failed output


## Hard stop B

If recall < 0.90:

STOP before composition.

Classify each recall failure as far as instrumentation permits:

- address failure
- value failure
- readout failure
- generation/output failure

Do not tune after observing the result.


## Phase C - Recursive reasoning test

ONLY if:

    addressing gate passes
    AND
    recall >= 0.90

Run the existing 24-question two-hop composition evaluation with thinking enabled.

Instrument the entire memory access sequence.

For each composition item determine:

1. Was the correct hop-1 fact addressed?
2. Was the correct intermediate recovered?
3. Did the intermediate appear in the reasoning trace?
4. After the intermediate appeared, did memory receive another meaningful query?
5. Did that query select a different and appropriate address?
6. Was the hop-2 fact retrieved?
7. Did the correct radiation appear in the trace?
8. Was the final answer correct?

This is the central experiment if Phase C is reached.


## Recursive-address success

The strongest result is NOT merely high final-answer accuracy.

The important observation would be:

    initial prompt
        ->
    address A
        ->
    retrieve intermediate X
        ->
    reasoning state contains X
        ->
    new query
        ->
    address B
        ->
    retrieve Y

where A and B correspond to the appropriate different facts.

That would demonstrate that retrieved parametric/external memory can alter the
reasoning state sufficiently to generate a second information-bearing memory
address.


## Interference

If Phase B is reached, evaluate the existing 12-question control set.

Report:

- control accuracy
- accuracy interference I
- changed answers
- substantive churn
- regressions
- repairs
- exact world-entity leakage
- ASCII world-shaped leakage
- Unicode-aware world-shaped leakage

Do not interpret a zero net I as zero behavioral interference.


## Detachability

Verify:

State 1:
    frozen base

State 2:
    memory installed but disabled

State 3:
    trained memory enabled

State 4:
    trained memory disabled

State 5:
    trained memory re-enabled

At gate = 0:

- logits must reproduce the frozen model
- control behavior must reproduce the frozen model
- memory knowledge must disappear if it was successfully learned

Re-enabling must restore the trained behavior.

Base weights must remain unchanged throughout.


## Required comparisons

Compare Experiment 007 with:

- Experiment 000 LoRA rank 16
- Experiment 002 LoRA rank 4
- Experiment 003 LoRA rank 8
- Experiment 004 isolated residual memory
- Experiment 005 explicit KV memory
- Experiment 006 anti-collapse KV memory

Do not compare downstream metrics for phases GOAL_7 never reached.

For example, if Phase A fails, do not pretend composition 0/24 is a meaningful
comparison. Composition was not tested.


## Required questions

The final report must answer:

1. Did direct address supervision prevent single-slot collapse?
2. How many dominant addresses were used across facts?
3. What was the largest fact share assigned to one address?
4. Was soft usage diversity different from hard address diversity?
5. Were addresses stable across held-out paraphrases?
6. Were addresses discriminative across different facts?
7. Did the positive addressing gate pass?
8. If it failed, why?
9. If it passed, could values be learned without destroying the address mapping?
10. Did recall reach 0.90?
11. For recall failures, where did the chain fail?
12. If Phase C was reached, did retrieved hop-1 information cause a second
    information-bearing query?
13. Did that second query select the correct hop-2 memory?
14. Was composition above chance?
15. What interference accompanied successful memory use, if any?
16. Was behavioral churn present beyond the net interference score?
17. Did gate = 0 reproduce frozen behavior?
18. Did unload/reload remain reversible?
19. What does GOAL_7 say about the original dynamic-memory hypothesis?
20. What single experiment is justified next?


## Outcomes

### Outcome A - Addressing fails

Direct supervision still cannot produce stable, discriminative addresses.

This is strong evidence against continuing this specific KV addressing mechanism.

Stop tuning it.


### Outcome B - Addressing works, storage fails

Fact identity can be represented as an address, but useful values cannot be attached
to those addresses through the current interface.

The bottleneck moves from addressing to value/readout integration.


### Outcome C - Addressing and recall work, recursive retrieval fails

The model can intentionally retrieve stored facts but retrieved information does not
become a useful second query.

This would finally isolate the recursive-memory problem directly.


### Outcome D - Recursive retrieval works but interference remains high

The complete memory chain exists, but touching the frozen reasoner still destabilizes
its existing computation.

The remaining problem is behavioral isolation.


### Outcome E - Recursive retrieval works with low interference

This is the target result.

It would establish, on this synthetic experiment, that a frozen pretrained reasoner
can:

- acquire detachable memory
- address it intentionally
- retrieve learned information
- incorporate that information into its reasoning state
- use the result to address memory again
- remove the memory and recover frozen behavior

This would justify replication before any larger architectural claims.


## Replication rule

Even Outcome E is not grounds for scaling immediately.

First replicate with:

- a second world seed
- a fresh training seed
- preferably jetson2 as the independent machine

The current program still rests primarily on one synthetic world.


## Stop condition

GOAL_7 ends when the first applicable condition occurs:

1. Addressing gate fails.
2. Addressing passes but recall gate fails.
3. Addressing and recall pass and the recursive-retrieval evaluation completes.

Do not tune after observing the result.

Do not begin GOAL_8.

Write:

    results/experiment_007/experiment_007_report.md

and wait for review.


## Principle

GOAL_5 asked next-token prediction to invent an address and failed.

GOAL_6 explicitly resisted collapse but regularized probability mass rather than
information-bearing selection and failed.

GOAL_7 removes that ambiguity.

Before asking whether memory can reason, prove that:

    the question determines the address.